簡(jiǎn)單介紹：
S500 Integrated Test System
詳情介紹：
Highly configurable, instrument-based system
Ideal for SMU-per-pin wafer level reliability (WLR) testing, high speed parallel test, die sorting and binning, NBTI, process control monitoring (PCM)
Intuitive test setup, data gathering and analysis with ACS software
Keithley's TSP-Link® backplane provides high speed measurement throughput
Flexible solution to meet emerging and mature testing needs
Full control of automated and semi-automated probers
Develop and execute tests at the device, site, wafer, and cassette level
